TFTs (thin-film transistors) have heretofore found wide acceptance in active-matrix liquid crystal displays, image sensors, and other devices packed on glass substrates. FIG. 6(A) is a schematic cross section of an insulated-gate field effect transistor (hereinafter simply referred to as a TFT) formed on a glass substrate. This TFT uses a thin-film silicon semiconductor formed on the glass substrate. A bottom layer 62 made of silicon oxide having a thickness of about 2000 .ANG. is formed on the glass substrate, indicated by 61. An active layer made of the silicon semiconductor film having source/drain regions 63, 65, and a channel formation region 64 is formed on the silicon oxide film 62. This silicon semiconductor film has a thickness of approximately 1000 .ANG. and is amorphous or crystalline (consisting of polycrystals or crystallites).
A silicon oxide film 66 forming a gate-insulating film is formed on the active layer to a thickness of about 1000 .ANG.. A gate electrode 67 is made of aluminum. An oxide layer 68 is formed out of aluminum around the gate electrode 67 to a thickness of about 2000 .ANG. by anodic oxidation. An interlayer insulator 69 is made of silicon oxide or the like. Contact holes 72 permitting contact with source/drain electrodes 70, 71 and with the gate electrode 67 are formed. The contact hole 72 for the gate electrode 67 is present on the rear side or front side of the plane of FIG. 6(A), i.e., is not coplanar with the source/drain electrodes 70 and 71.
The structure shown in FIG. 6(A) is characterized in that an offset gate region is formed by a self-aligning process because of the thickness 73 of the oxide layer 68 around the gate electrode 67, the oxide layer 68 being formed by anodic oxidation of the gate electrode 67 of aluminum. In particular, after the oxide layer 68 is formed, impurity ions are implanted to form the source/drain regions. Therefore, a region corresponding to the thickness of the oxide layer 68 can be formed as an offset region.
In practice, however, the impurities diffuse themselves and so the boundary between the source/drain regions 63, 65 and the channel formation region 64 is offset toward the channel formation region from the location corresponding to the end of the oxide layer 68. Therefore, the thickness of the oxide layer 68 must be determined, taking this into consideration. That is, it is common practice to make the thickness of the oxide layer 68 larger than the length of the given offset gate.
When the contact holes for the source/drain regions 63, 65 are formed, if overetching is done, the portions surrounding the contact holes are overetched around the interface with the silicon oxide film 66. If aluminum electrodes 70 and 71 are subsequently formed, aluminum atoms diffuse to the surrounding etched portions. Sometimes, aluminum atoms diffuse close to the channel formation region 64, thus deteriorating the characteristics and the reliability of the TFT.
On the other hand, where the distance 74 between the contact portion for the source/drain region and the channel formation region 64 is larger, the sheet resistance of the source/drain region poses problems. One conceivable method of solving this problem is to reduce the distance indicated by 74. However, the distance cannot be reduced greatly because of the accuracy of mask alignment. Especially, where the used substrate is made of glass, shrinkage of the glass substrate caused during a heating step presents problems. Hence, the accuracy of mask alignment results in serious problems. For example, if a glass substrate 10 cm or more square is heated to about 600.degree. C., the substrate shrinks easily by about several micrometers. Therefore, the present situation is that the distance indicated by 74 contains a margin of approximately 20 .mu.m.
Where the problems with overetching caused during formation of the contact holes for the source/drain regions are considered, it is impossible to reduce the distance 74 by a great extent. As described thus far, the prior art TFTs suffer from two problems; (1) The formation of the contact holes for the source/drain regions presents problems; and (2) In association with (1), the contact holes cannot be formed close to the channel formation region; Consequently, the sheet resistance of the source/drain regions poses problems.
A TFT of a structure as shown in FIG. 6(B) has been proposed as a structure free from the problems (1) and (2) with the TFT shown in FIG. 6(A). This TFT has a gate electrode 67 consisting mainly of aluminum in the same way as the TFT shown in FIG. 6(A). An oxide layer 68 is formed around the gate electrode 67 by anodic oxidation. Source/drain electrodes 70 and 71 are formed in intimate contact with the oxide layer 68. In this structure, it is inevitable that the oxide layer 68 is interposed between the source/drain electrodes 70, 71 and the gate electrode 67. Therefore, parasitic capacitance induced by the presence of the intervening oxide layer 68 presents a problem. That is, the operation is made unstable and the reliability deteriorates. The above problem may be solved by increasing the thickness of the oxide layer 68. However, it is impossible to increase the thickness greatly, because the thickness of the oxide layer 68 determines the length of the offset gate.